奈米工程與微系統研究所　書報討論

Seminar of Inst. NanoEngineering and MicroSystems

2014年10月20日，下午1530－1710，工程一館１０８室

1530-1710 on Oct. 20, 2014 in Room 108 of Engineering Building I

演講者：鄭裕庭

Speaker：Yu-Ting Cheng

任職單位：交通大學

Affiliation：National Chiao Tung University

Topic：Low Temperature Wafer Level Processes -An Integration Paradigm for Microsystem Fabrication

Abstract

For the technology development in microsystem fabrication, how to make everything together merely using the state-of-the-art CMOS processing techniques is always a critical research subject. In the decades, several Si-based micromachining techniques, such as silicon isotropically and anisotropically etching, electroplating, and wafer bonding, wafer level fabrication process.…etc, have advanced the real practice of “Heterogeneous Integration” for integrated microsystem fabrication. Not only small form factor, low parasitic effect, and low power consumption but also low manufacturing cost with high performance and multi-functions can be realized to achieve the ultimate goal of SOC (System-on-a-Chip) by the attempt.  In this talk, I would like to share an integration paradigm with you for microsystem fabrication by showing our past research works.  Abided by the “low temperature” and “wafer level” process criterion, you will find a R&D pathway in paving the way of microsystem fabrication for the realization of More-than-Moore era.

Contact: Chen Yu Ju, #80627, cues91225@gmail.com